The present invention generally relates to optimizing layer thickness on a single wafer a using CMP process to facilitate the lithography and etch process.
In the field of microelectronics, layers of various materials are commonly formed over wafers or other substrates. Such materials include polymers,oxides, nitrides, metals, and semiconductors (e.g., polysilicon). It is common to etch structures, such as vias and trenches, through one or more of the layers at desired locations in constructing various electrical structures and semiconductor devices. Formation of such structures requires removal of some portions of a material layer.
Material is removed by etching through an etch-resistant mask with either a chemical etchant (wet etching) or with a dry etching process, such as reactive ion etching (RIE) or plasma etching. The etch mask has a pattern generally conforming to the structures to be formed. Generally, anisotropic etching processes are preferred for fine structures since they allow the structure to conform to the mask patterns. Nonetheless, no process is completely anisotropic and, thus, undercutting and other variations between the etched pattern and the mask will occur.
The degree to which a given process is anisotropic depends upon the processing conditions (e.g., temperature, relative concentrations of the etchant""s chemical components, agitation rate, plasma energy). The etch rates also depend upon the area of the mask aperture for the structure, the thickness of the layer to be etched and the depth of the structure, particularly for structures formed through relatively small apertures. It is often necessary to determine the optimum set of processing conditions and etch time for forming a structure in a particular thickness of material layer. This optimization methodology usually requires conducting a number of split runs with a set of test parameters (each test run using a different thickness of layer, set of processing conditions and/or etch parameters), and examining the resulting structures.
The ever increasing demand for miniaturization in the field of integrated circuits results in a corresponding demand for increased device density. Moreover, market forces are creating a need to improve device yield per wafer. As a result, larger wafers (e.g., 14xe2x80x3 diameter) are being used to yield more devices per wafer. However, as the size of the wafers increase so does the relative cost of the wafer. As noted above, process optimization typically requires conducting a number of trial processing runs to determine an optimal process layer thickness for mass production of devices. Conventionally, a test material layer 10 is formed on a single wafer 20 as shown in FIG. 1 and a test run is performed to optimize a process related thereto. Many factors including the thickness of the material layer 10 play a role in achieving an optimal process for device production. Generally, after each test, the test wafer 20 is discarded and another wafer is employed in running another test with slightly different test conditions. Such iterations are repeatedly conducted until a substantially optimal process is determined.
As can be appreciated, such iterative testing results in many test wafers being employed which adds to the cost of process optimization especially when considering the increased costs associated with large size wafers. Accordingly, there is a need in the art for a method of conducting process optimization which conserves the number of test wafers employed.
The present invention provides for a method for facilitating process optimization which conserves the number of test wafers employed as compared to conventional process optimization techniques. In the method, a material layer is formed on a test wafer. The material layer is segmented into N number of regions, and each of the regions has a thickness different from the other regions. The differences in thicknesses of the regions may be achieved by performing a chemical mechanical polishing process on the respective regions to achieve different degrees of material layer thicknesses thereof. After the various regions are complete in relavent part, process optimization tests are performed on the test wafer. Since there are N regions (each having a different material layer thickness) the number of separate process optimization tests performed in connection with material layer thickness are significantly reduced as compared to conventional techniques.
Conventionally, process optimization tests for N number of material layer thicknesses typically required using N number of test wafers. The present invention provides for using a test wafer with N number of regions of material layer (each region having a different thickness than the other regions), which affords for substantial reduction in the number of test wafers employed in process optimization test runs relating to material layer thickness.
One specific aspect of the present invention relates to a test wafer for use in optimizing a process. The test wafer includes a substrate and a material layer formed over the substrate. The material layer includes N number of test regions (N being an integer greater than one). At least one of the test regions has a material layer thickness different from another of the test regions.
Another aspect of the present invention relates to a system for facilitating process optimization. The system includes: a test wafer which includes: a substrate; and a material layer formed over the substrate. The material layer includes N number of test regions (N being an integer greater than one). At least one of the test regions has a material layer thickness different from another of the test regions. The system further includes a process analyzer operatively coupled to the test wafer to collect test data relating to a process test run being performed on the test wafer. The process analyzer includes a microprocessor for analyzing the test data. The system determines an optimal material layer thickness from among the test regions for the process test run.
Still another aspect of the present invention relates to a system for creating a test wafer having a material layer including N number of test regions (N being an integer greater than one). At least one of the test regions has a material layer thickness different from another of the test regions. The system includes: a spindle drive system for driving a plurality of spindles, each spindle having first and second ends, the first ends being operatively coupled to the spindle drive system and the second ends being operatively coupled to polishing pads, respectively. The polishing pads are employed in forming the test regions.
Another aspect of the present invention relates to a system for creating a test wafer having a material layer including N number of test regions (N being an integer greater than one), at least one of the test regions having a material layer thickness different from another of the test regions. The system includes: a spindle drive system for driving at least one spindle, the at least one spindle having first and second ends, the first end being operatively coupled to the spindle drive system and the second end being operatively coupled to a polishing pad. The polishing pad is employed in forming the test regions.
Yet another aspect of the present invention relates to a method of forming a test wafer. A material layer is formed on a substrate; and a chemical mechanical polishing (CMP) process is performed to form a plurality of test regions in the material layer, at least one of the test regions having a material layer thickness different from another test region.
Still another aspect of the present invention relates to a system for creating a test wafer having a material layer including N number of test regions (N being an integer greater than one), at least one of the test regions having a material layer thickness different from another of the test regions. The system includes means for forming a first region of the test regions to have a material layer thickness equal to T1 and forming a second region of the test regions to have a material layer thickness of T2, wherein T1 greater than T2.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.